1. Field of the Invention
The present invention relates to a method for connecting a DRAM module to a DRAM included in a higher-order control system of a full electronic exchange, and more particularly to a method for connecting a DRAM module to memory portions of a main processor and memory management PCB board assembly (MPMA PBA) included in a main processor hardware (MPH) block and adapted to perform a higher-order control in a full electronic exchange.
2. Description of the Prior Art
Generally, DRAM's used in higher-order control systems of full electronic exchanges have a troublesomeness in expanding their memory capacity because they are fixed to 16 M bytes. This will be described in detail in conjunction with FIG. 1 which shows the relationship between a DRAM included in an MPMA and a central processing unit serving to define memory areas of the DRAM. As shown in FIG. 1, the MPMA includes the central processing unit, which is denoted by the reference numeral 1. The central processing unit 1 serves to control various units of the MPMA. The MPMA further includes an address bus 2 for transmitting address data output from the central processing unit 1 to desired units of the MPMA, and a data bus 3 for transmitting real data output from the central processing unit 1 to desired units of the MPMA. A control signal generating unit 4 is also provided which serves to receive a control signal from the central processing unit 1, thereby outputting control signals selecting respective memory areas of DRAM's 5 and 6 which are also included in the MPMA. The DRAM 5 is stored with practical programs required for the system whereas the DRAM 6 is a 16-bit parity DRAM. To the MPMA, a dependent MPMA is connected, which has the same arrangement as the MPMA. Thus, a double MPMA arrangement is obtained.
The double MPMA arrangement obtained by the dependant MPMA means that it can carry out either a main operation or dependent operation in accordance with the situation. In this arrangement, the main MPMA has a circuit arrangement enabling both reading and writing.
Each DRAM used in the MPMA having the above-mentioned arrangement is a zigzag-in-line package type RAM. This RAM has a total memory area of 4 M.times.36 bits including a data area of 4 m.times.32 bits and a parity area of 4 M.times.4 bits.
The control signal output from the central processing unit 1 is applied to the control signal generating unit 4 which, in turn, converts the signal into control signals for respectively selecting memory areas of the DRAM's 5 and 6.
The inner memory area of the data DRAM 5 is divided into a plurality of sub-areas each having a memory capacity of 4 bytes. Hereinafter, such a sub-area will be referred to as "a bank". The data DRAM 5 includes four banks.
These banks are selected in accordance with associated control signals output from the control signal generating unit 4, respectively. These control signals for selecting the banks of the data DRAM 5 are signals CAS0, CAS1, CAS2 and CAS3, respectively.
All banks of the data DRAM 5 are commonly coupled to a control signal RAS output from the control signal generating unit 4. This RAS signal is used in combination with each CAS signal. Each unit bank is constructed to carry out its 8-, 16- and 32-bit data transmitting operations in accordance with respective signals, WE0, WE1, WE2 and WE3, for writing operations along with an OE signal for reading operations. The reason why each unit bank enables such data transmitting operations is because the zigzag-in-line package type DRAM has a structure including RAS, CAS, WE and OE. All the above-mentioned signals are adapted to operate in a low level (designated "active low" or "/").
The parity DRAM 6 has a memory area having a 16 M-bit size and operates a control signal CASP. This parity DRAM 6 is stored with parity data corresponding to each 8-bit data stored in the data DRAM 5. When data is written on the data DRAM 5, parity data associated with the data being written on the data DRAM 5 is also written on the parity DRAM 6. When the data stored in the data DRAM 5 is read, the data stored in the parity DRAM 6 is also read to determine whether the data read out of the data DRAM 5 is normal or has errors.
In terms of the memory area, the data DRAM 5 and parity DRAM 6 have the relationship that the parity DRAM 6 always requires its entire memory area, namely, a 16 M-bit memory area irrespective of whether the memory area of the data DRAM 5 being used is a 4 M- or 16 M-byte bank.
However, this is a considerable economical loss. Even though the memory capacity of the data DRAM 5 increases using the same circuit as the memory thereof, the parity DRAM 6 still involve the waste of its memory.
Meanwhile, many of full electronic exchanges being presently used require DRAM's for MPMA PBA which have a memory size of larger than 16 M bytes. Furthermore, this requirement is on an increasing trend. For higher-order control systems requiring a memory size of larger than 16 M bytes, a PBA, which is a separate board called "MECA", is used in addition to the data DRAM 5 because the data DRAM 5, which has a divided construction, is fixed to 16 M bytes. This PBA serves to expand the memory size from the 16 M-byte size.
Taking into consideration the double MPMA arrangement, two PBA boards which have the same size as the MPMA PBA are required. In accordance with this method, however, the MPMA PBA can not expand its memory size by itself.